HDMIc Test

When performing HDMI display in a Linux environment, we need to modify the previously created Vivado file.

Modifying the Vivado Project

Enable both IICs and configure them to EMIO mode:

Configure interrupts, enable IRQ_F2P to receive interrupts from the PL side

Add a dynamic clock controller. The main function of this module is to configure different clock outputs based on different resolutions. This module's clock must be configured to 100MHz.

Add your own IP cores:

Here we need to add two custom IP cores:

Refer to the HDMI test content from the bare-metal system, replace the clk_wiz core with the dynclk core. Right-click on Block Design and click "+" to search:

Keep the related configurations as default:

Add an HDMI encoder to convert RGB data to TMDS signals.

Search and add our custom rgb and make the TMDS Make External

Add a vector inverter:

Connect the interrupt signals. First, add a Concat IP for interrupt signal connection.

Connect the clock signals that Vivado may not automatically connect.

Use Vivado's auto-connect feature to complete the remaining wire connections. Select all modules for auto-connection.

After saving the design, validate it. Add the XDC file for HDMI output to constrain the pins.

​x
set_property PACKAGE_PIN M14 [get_ports {GPIO_0_0_tri_io[0]}]
set_property PACKAGE_PIN M15 [get_ports {GPIO_0_0_tri_io[1]}]
set_property PACKAGE_PIN N15 [get_ports {GPIO_0_0_tri_io[2]}]
set_property PACKAGE_PIN N16 [get_ports {GPIO_0_0_tri_io[3]}]
set_property PACKAGE_PIN K18 [get_ports {GPIO_0_0_tri_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[0]}]

set_property PACKAGE_PIN G14 [get_ports CAN_0_0_rx]
set_property PACKAGE_PIN J15 [get_ports CAN_0_0_tx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_0_rx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_0_tx]

#set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl_0]
#set_property PACKAGE_PIN F16 [get_ports reset_rtl_0]

set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN L14 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN L15 [get_ports IIC_0_0_scl_io]

set_property PACKAGE_PIN F19 [get_ports MDIO_PHY_0_mdc]
set_property PACKAGE_PIN F20 [get_ports MDIO_PHY_0_mdio_io]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_0_mdc]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_0_mdio_io]
set_property PACKAGE_PIN E18 [get_ports {RGMII_0_rd[0]}]
set_property PACKAGE_PIN E19 [get_ports {RGMII_0_rd[1]}]
set_property PACKAGE_PIN D18 [get_ports {RGMII_0_rd[2]}]
set_property PACKAGE_PIN E17 [get_ports {RGMII_0_rd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_tx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_txc]
set_property PACKAGE_PIN A20 [get_ports {RGMII_0_td[0]}]
set_property PACKAGE_PIN B20 [get_ports {RGMII_0_td[1]}]
set_property PACKAGE_PIN C20 [get_ports {RGMII_0_td[2]}]
set_property PACKAGE_PIN D19 [get_ports {RGMII_0_td[3]}]
set_property PACKAGE_PIN H17 [get_ports RGMII_0_rx_ctl]
set_property PACKAGE_PIN H16 [get_ports RGMII_0_rxc]
set_property PACKAGE_PIN D20 [get_ports RGMII_0_tx_ctl]
set_property PACKAGE_PIN B19 [get_ports RGMII_0_txc]

set_property SLEW FAST [get_ports {RGMII_0_td[0]}]
set_property SLEW FAST [get_ports {RGMII_0_td[1]}]
set_property SLEW FAST [get_ports {RGMII_0_td[2]}]
set_property SLEW FAST [get_ports {RGMII_0_td[3]}]
set_property SLEW FAST [get_ports RGMII_0_tx_ctl]
set_property SLEW FAST [get_ports RGMII_0_txc]

create_clock -period 8.000 -name RGMII_0_rxc -waveform {0.000 4.000} [get_ports RGMII_0_rxc]
set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {gmii_clk_25m_out gmii_clk_2_5m_out}] -group [get_clocks -include_generated_clocks gmii_clk_125m_out]

set_property PACKAGE_PIN K14 [get_ports UART_1_0_txd]
set_property PACKAGE_PIN J14 [get_ports UART_1_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_0_txd]

set_property PACKAGE_PIN V5 [get_ports {gpio_rtl_2_tri_io[22]}]
set_property PACKAGE_PIN Y13 [get_ports {gpio_rtl_2_tri_io[21]}]
set_property PACKAGE_PIN Y6 [get_ports {gpio_rtl_2_tri_io[20]}]
set_property PACKAGE_PIN Y8 [get_ports {gpio_rtl_2_tri_io[19]}]
set_property PACKAGE_PIN W8 [get_ports {gpio_rtl_2_tri_io[18]}]
set_property PACKAGE_PIN U8 [get_ports {gpio_rtl_2_tri_io[17]}]
set_property PACKAGE_PIN W9 [get_ports {gpio_rtl_2_tri_io[16]}]
set_property PACKAGE_PIN V10 [get_ports {gpio_rtl_2_tri_io[15]}]
set_property PACKAGE_PIN U5 [get_ports {gpio_rtl_2_tri_io[14]}]
set_property PACKAGE_PIN V6 [get_ports {gpio_rtl_2_tri_io[13]}]
set_property PACKAGE_PIN V7 [get_ports {gpio_rtl_2_tri_io[12]}]
set_property PACKAGE_PIN W11 [get_ports {gpio_rtl_2_tri_io[11]}]
set_property PACKAGE_PIN T9 [get_ports {gpio_rtl_2_tri_io[10]}]
set_property PACKAGE_PIN Y12 [get_ports {gpio_rtl_2_tri_io[9]}]
set_property PACKAGE_PIN Y7 [get_ports {gpio_rtl_2_tri_io[8]}]
set_property PACKAGE_PIN Y9 [get_ports {gpio_rtl_2_tri_io[7]}]
set_property PACKAGE_PIN V8 [get_ports {gpio_rtl_2_tri_io[6]}]
set_property PACKAGE_PIN U9 [get_ports {gpio_rtl_2_tri_io[5]}]
set_property PACKAGE_PIN W10 [get_ports {gpio_rtl_2_tri_io[4]}]
set_property PACKAGE_PIN V11 [get_ports {gpio_rtl_2_tri_io[3]}]
set_property PACKAGE_PIN T5 [get_ports {gpio_rtl_2_tri_io[2]}]
set_property PACKAGE_PIN W6 [get_ports {gpio_rtl_2_tri_io[1]}]
set_property PACKAGE_PIN U7 [get_ports {gpio_rtl_2_tri_io[0]}]
set_property PACKAGE_PIN W19 [get_ports {gpio_rtl_0_tri_io[31]}]
set_property PACKAGE_PIN Y14 [get_ports {gpio_rtl_0_tri_io[30]}]
set_property PACKAGE_PIN W14 [get_ports {gpio_rtl_0_tri_io[29]}]
set_property PACKAGE_PIN Y16 [get_ports {gpio_rtl_0_tri_io[28]}]
set_property PACKAGE_PIN Y17 [get_ports {gpio_rtl_0_tri_io[27]}]
set_property PACKAGE_PIN Y18 [get_ports {gpio_rtl_0_tri_io[26]}]
set_property PACKAGE_PIN Y19 [get_ports {gpio_rtl_0_tri_io[25]}]
set_property PACKAGE_PIN W20 [get_ports {gpio_rtl_0_tri_io[24]}]
set_property PACKAGE_PIN V20 [get_ports {gpio_rtl_0_tri_io[23]}]
set_property PACKAGE_PIN U20 [get_ports {gpio_rtl_0_tri_io[22]}]
set_property PACKAGE_PIN T20 [get_ports {gpio_rtl_0_tri_io[21]}]
set_property PACKAGE_PIN T19 [get_ports {gpio_rtl_0_tri_io[20]}]
set_property PACKAGE_PIN T15 [get_ports {gpio_rtl_0_tri_io[19]}]
set_property PACKAGE_PIN T14 [get_ports {gpio_rtl_0_tri_io[18]}]
set_property PACKAGE_PIN T16 [get_ports {gpio_rtl_0_tri_io[17]}]
set_property PACKAGE_PIN U17 [get_ports {gpio_rtl_0_tri_io[16]}]
set_property PACKAGE_PIN P14 [get_ports {gpio_rtl_0_tri_io[15]}]
set_property PACKAGE_PIN R14 [get_ports {gpio_rtl_0_tri_io[14]}]
set_property PACKAGE_PIN R16 [get_ports {gpio_rtl_0_tri_io[13]}]
set_property PACKAGE_PIN R17 [get_ports {gpio_rtl_0_tri_io[12]}]
set_property PACKAGE_PIN V15 [get_ports {gpio_rtl_0_tri_io[11]}]
set_property PACKAGE_PIN W15 [get_ports {gpio_rtl_0_tri_io[10]}]
set_property PACKAGE_PIN P19 [get_ports {gpio_rtl_0_tri_io[9]}]
set_property PACKAGE_PIN N18 [get_ports {gpio_rtl_0_tri_io[8]}]
set_property PACKAGE_PIN U19 [get_ports {gpio_rtl_0_tri_io[7]}]
set_property PACKAGE_PIN U18 [get_ports {gpio_rtl_0_tri_io[6]}]
set_property PACKAGE_PIN P16 [get_ports {gpio_rtl_0_tri_io[5]}]
set_property PACKAGE_PIN P15 [get_ports {gpio_rtl_0_tri_io[4]}]
set_property PACKAGE_PIN T17 [get_ports {gpio_rtl_0_tri_io[3]}]
set_property PACKAGE_PIN R18 [get_ports {gpio_rtl_0_tri_io[2]}]
set_property PACKAGE_PIN P18 [get_ports {gpio_rtl_0_tri_io[1]}]
set_property PACKAGE_PIN N17 [get_ports {gpio_rtl_0_tri_io[0]}]
set_property PACKAGE_PIN Y11 [get_ports {gpio_rtl_1_tri_io[31]}]
set_property PACKAGE_PIN U10 [get_ports {gpio_rtl_1_tri_io[30]}]
set_property PACKAGE_PIN T11 [get_ports {gpio_rtl_1_tri_io[29]}]
set_property PACKAGE_PIN U14 [get_ports {gpio_rtl_1_tri_io[28]}]
set_property PACKAGE_PIN V12 [get_ports {gpio_rtl_1_tri_io[27]}]
set_property PACKAGE_PIN U12 [get_ports {gpio_rtl_1_tri_io[26]}]
set_property PACKAGE_PIN M17 [get_ports {gpio_rtl_1_tri_io[25]}]
set_property PACKAGE_PIN L20 [get_ports {gpio_rtl_1_tri_io[24]}]
set_property PACKAGE_PIN K19 [get_ports {gpio_rtl_1_tri_io[23]}]
set_property PACKAGE_PIN G17 [get_ports {gpio_rtl_1_tri_io[22]}]
set_property PACKAGE_PIN H18 [get_ports {gpio_rtl_1_tri_io[21]}]
set_property PACKAGE_PIN J16 [get_ports {gpio_rtl_1_tri_io[20]}]
set_property PACKAGE_PIN T10 [get_ports {gpio_rtl_1_tri_io[19]}]
set_property PACKAGE_PIN U15 [get_ports {gpio_rtl_1_tri_io[18]}]
set_property PACKAGE_PIN W13 [get_ports {gpio_rtl_1_tri_io[17]}]
set_property PACKAGE_PIN T12 [get_ports {gpio_rtl_1_tri_io[16]}]
set_property PACKAGE_PIN M18 [get_ports {gpio_rtl_1_tri_io[15]}]
set_property PACKAGE_PIN L19 [get_ports {gpio_rtl_1_tri_io[14]}]
set_property PACKAGE_PIN J19 [get_ports {gpio_rtl_1_tri_io[13]}]
set_property PACKAGE_PIN G18 [get_ports {gpio_rtl_1_tri_io[12]}]
set_property PACKAGE_PIN J18 [get_ports {gpio_rtl_1_tri_io[11]}]
set_property PACKAGE_PIN K16 [get_ports {gpio_rtl_1_tri_io[10]}]
set_property PACKAGE_PIN R19 [get_ports {gpio_rtl_1_tri_io[9]}]
set_property PACKAGE_PIN P20 [get_ports {gpio_rtl_1_tri_io[8]}]
set_property PACKAGE_PIN N20 [get_ports {gpio_rtl_1_tri_io[7]}]
set_property PACKAGE_PIN V16 [get_ports {gpio_rtl_1_tri_io[6]}]
set_property PACKAGE_PIN W16 [get_ports {gpio_rtl_1_tri_io[5]}]
set_property PACKAGE_PIN U13 [get_ports {gpio_rtl_1_tri_io[4]}]
set_property PACKAGE_PIN V13 [get_ports {gpio_rtl_1_tri_io[3]}]
set_property PACKAGE_PIN V17 [get_ports {gpio_rtl_1_tri_io[2]}]
set_property PACKAGE_PIN V18 [get_ports {gpio_rtl_1_tri_io[1]}]
set_property PACKAGE_PIN W18 [get_ports {gpio_rtl_1_tri_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[31]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[30]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[29]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[28]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_极[26]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[25]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_极_tri_io[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[23]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_极_tri_io[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[13]}]
set_property IOSTANDARD LVCMOS33 [get_极 {gpio_rtl_1_tri_io[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_t极_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[3]}]
set极 IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_1_tri_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[31]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[30]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[29]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[28]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[26]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[25]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gp极_rtl_0_tri_io[23]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[极]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_t极_io[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[18]}]
set_property IOSTANDARD LVCMOS33 [极_ports {gpio_rtl_2_tri_io[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rt极_tri_io[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[极]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_2_tri_io[0]}]

set_property PACKAGE_PIN J20 [get_ports {TMDS_0_data_p[0]}]
set_property PACKAGE_PIN G19 [get_ports {TMDS_0_data_p[1]}]
set_property PACKAGE_PIN M19 [get_ports {TMDS_0_data_p[2]}]

set_property PACKAGE_PIN L16 [get_ports TMDS_极_clk_p]

set_property PACKAGE_PIN F16 [get_ports IIC_1_0_sda_io]
set_property PACKAGE_PIN H15 [get_ports IIC_1_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_sda_io]

Compile to generate the bit file, then export the .xsa file.

Import Hardware Configuration

Import the hardware obtained from the above steps into the petalinux project directory.

Open a terminal in this directory and enter the petalinux environment.

xxxxxxxxxx
mind@Ubuntu20:~/petalinux_projects/petalinux-mind$ speta
PetaLinux environment set to '/opt/pkg/petalinux/2021.1'
WARNING: This is not a supported OS
INFO: Checking free disk space
INFO: Checking installed tools
INFO: Checking installed development libraries
INFO: Checking network and other services

Create modules for Digilent DynClk and Digilent HDMI: clk-dglnt-dynclk, digilent-hdmi

xxxxxxxxxx
mind@Ubuntu20:~/petalinux_projects/petalinux-mind$ petalinux-create -t modules --name clk-dglnt-dynclk --enable
INFO: Create modules: clk-dglnt-dynclk
#Path to generated files
INFO: New modules successfully created in /home/mind/petalinux_projects/petalinux-mind/project-spec/meta-user/recipes-modules/clk-dglnt-dynclk     
INFO: Enabling created component...
INFO: Sourcing build environment
INFO: Silentconfig rootfs
INFO: clk-dglnt-dynclk has been enabled 
mind@Ubuntu20:~/petalinux_projects/petalinux-mind$ petalinux-create -t modules --name digilent-hdmi --enable
INFO: Create modules: digilent-hdmi
#Path to generated files
INFO: New modules successfully created in /home/mind/petalinux_projects/petalinux-mind/project-spec/meta-user/recipes-modules/digilent-hdmi
INFO: Enabling created component...
INFO: Sourcing build environment
INFO: Silentconfig rootfs
INFO: digilent-hdmi has been enabled 

In the project folder, copy digilent_hdmi.c and clk-dglnt-dynclk.c, and replace the content of the automatically generated module .c files.

xxxxxxxxxx
#clk-dglnt-dynclk.c path
project-spec/meta-user/recipes-modules/clk-dglnt-dynclk/files
#digilent_hdmi.c path
project-spec/meta-user/recipes-modules/digilent-encoder/files

i. Note that the file uses a dash (“-“) and not and underscore (“_”).
ii. You may need to add these two include lines to the digilent-hdmi.c file:
1. #include <drm/drm_edid.h>
2. #include <linux/i2c.h>

Import Hardware

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mind@Ubuntu20:~/petalinux_projects/petalinux-mind$ petalinux-config --get-hw-description=.

Modify Kernel

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petalinux-config -c kernel
# Enable the following sections ( "*" )
Device Drivers → Graphics support
               ---->Xilinx DRM KMS Driver
               ---->Xilinx DRM KMS bridge
               ---->Xilinx DRM PL display driver
               ---->Xilinx DRM VTC Driver
               ---->Frame Buffer Devices
                    ---->Support for Frame Buffer Devices
               ---->Console display driver support
                    ---->Framebuffer Console support
               → IIC support
               ---->I2C support\I2C Hardware Bus Support\Xilinx I2C Controller
               → Multimedia support
               ---->Media drivers\Media USB Adapters
               → Character devices
               ---->Enable TTY
               ---->Virtual terminal
               ---->Support for binding and unbinding console drivers
Cryptographic API → SHA-224 and SHA-256 digest algorithm

Modify Device Tree

Open the file named system-user.dtsi in the petalinux project file.

Modify the device tree content as follows.

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/include/ "system-conf.dtsi"


/ {
    model = "Mind-Z7020";
};

/ {
    usb_phy0: phy0@e0002000 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
&usb0 {
    dr_mode = "otg";
    /*dr_mode = "peripheral";*/
    usb-phy = <&usb_phy0>;
    usb-reset = <&gpio0 10 0>;
};


&gem0 {
    phy-handle = <&phy0>;

    phy0: phy@4 {
        device_type = "ethernet-phy";
        reg = <0x4>;
    };
};


&gem1 {
    gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;
    phy-mode = "gmii";
    status = "okay";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
    ps7_ethernet_1_mdio: mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        gmii_to_rgmii_0: gmii_to_rgmii_0@8 {
            compatible = "xlnx,gmii-to-rgmii-1.0";
            phy-handle = <&phy1>;
            reg = <8>;
        };
        phy1: phy@0 {
            reg = <0>;
            device_type = "ethernet-phy";
        };
    };
};


&axi_dynclk_0 {
    compatible = "dglnt,axi-dynclk";
    #clock-cells = <0>;
    clocks = <&clkc 15>;
};

&v_tc_0 {
    compatible = "xlnx,bridge-v-tc-6.1";
    xlnx,pixels-per-clock = <1>;
};


&amba_pl {
    digilent_hdmi {
        compatible = "digilent,hdmi";
        clocks = <&axi_dynclk_0>;
        clock-names = "clk";
        digilent,edid-i2c = <&i2c1>;
        digilent,fmax = <150000>;
        port@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            hdmi_ep: endpoint {
                remote-endpoint = <&pl_disp_ep>;
            };
        };
    };

    xlnx_pl_disp {
        compatible = "xlnx,pl-disp";
        dmas = <&axi_vdma_0 0>;
        dma-names = "dma0";
        xlnx,vformat = "RG24";
        xlnx,bridge = <&v_tc_0>;
        port@0 {
            reg = <0>;
            pl_disp_ep: endpoint {
                remote-endpoint = <&hdmi_ep>;
            };
        };
    };
};

&i2c1 {
    clock-frequency = <100000>;
};

Modify U-Boot

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petalinux-config -c u-boot

# Enable the following sections ( "*" )
Device Drivers → Graphics support
               ---->Enable driver model support for LCD/video
               ---->Enable Display support

Compile and Package

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petalinux-build
petalinux-package --boot --fsbl ./images/linux/zynq_fsbl.elf --u-boot --fpga --force

• Copy BOOT.BIN, boot.scr, and image.ub from the project directory images -> linux to the FAT partition of the TF card.

• Extract the ./image/rootfs.tar.gz file to the second partition.

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sudo tar -xzf ./images/linux/rootfs.tar.gz -C /media/mind/rootfs/
sync

• Unmount the TF card.

• Set the development board to SD mode startup, connect the HDMI display, and start the development board. The display result can be directly observed.